Description: 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能，简单易懂，并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file Platform: |
Size: 1024 |
Author:汪艳婷 |
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Description: 同步fifo设计，仿真已通过，用Verilog编写，代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short Platform: |
Size: 1024 |
Author:xinghuo |
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Description: 同步fifo设计，仿真已通过，用Verilog编写，代码短小，易懂-Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand Platform: |
Size: 1024 |
Author:xinghuo |
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Description: 0.最简单的SystemC程序：hello, world.
1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。
2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。
3.如何在SystemC中实现延时（类似verilog中的#time）的例子。
4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。
5.构造函数带参数的例子。
6.轮转仲裁的例子。
7.使用类摸板的例子。
8.如何在模块中包含子模块。
9.SystemC的Transaction级验证示例。
10.如何trace一个数组
11.SystemC中使用测试向量文件输入的例子。
12.SystemC采用UDP/TCP通信的例子。
13.Cadence的ncsc的例子。
-0 most simple SystemC program: hello, world.
A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files.
Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated.
Delay (similar to verilog# time). In SystemC examples.
4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal.
Constructor with parameters example.
(6) examples of web arbitration.
7. The class Moban examples.
8 module contains a sub-module.
9.SystemC of Transaction-Level Verification example.
10 How to trace an array
11.SystemC use the example of the test vector file input.
12.SystemC using the example of the UDP/TCP communication.
Examples of 13.Cadence the ncsc. Platform: |
Size: 532480 |
Author:sdd |
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Description: 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure. Platform: |
Size: 5120 |
Author:dean |
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Description: 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references Platform: |
Size: 1715200 |
Author:gt |
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Description:
本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into TPRAM, DPRAM, TPRAM read one each port, a port read-only, write-only another port, DPRAM read each one each port, each port can either be read. This article synchronous FIFO is TPRAM (two-port RAM, a read a write). Platform: |
Size: 650240 |
Author:jodyql |
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Search - synchronous fifo verilog